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CDB4362 Evaluation Board for CS4362
Features
l Demonstrates
Description
The CDB4362 evaluation board is an excellent means for quickly evaluating the CS4362 24-bit, six channel D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS4362 (for control port mode only) and a power supply. Analog line level outputs are provided via RCA phono jacks. The CS8414 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog converter and will accept S/PDIF and EIAJ-340 compatible audio data. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. ORDERING INFORMATION CDB4362 Evaluation Board
recommended layout and grounding arrangements l CS8414 receives S/PDIF & EIAJ-340 compatible digital audio l Headers for external audio input for either PCM or DSD l Requires only a digital signal source and power supplies for a complete Digital-toAnalog-Converter system
Control Port Inputs for PCM Clocks and Data
CS8414 Digital Audio Interface CS4362
Analog Outputs
Inputs for DSD Data and Clock
M UTE
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved)
OCT `01 DS257DB1 1
CDB4362
TABLE OF CONTENTS
1. 2. 3. 4. 5. 6. 7. 8. 9. CS4362 DIGITAL TO ANALOG CONVERTER ........................................................................ 3 CS8414 DIGITAL AUDIO RECEIVER ...................................................................................... 3 INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 3 POWER SUPPLY CIRCUITRY ................................................................................................. 3 GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 3 CONTROL PORT SOFTWARE ................................................................................................ 3 DSD OPERATION .................................................................................................................... 4 ANALOG OUTPUT FILTER ..................................................................................................... 4 ERRATA ................................................................................................................................... 5
LIST OF FIGURES
Figure 1. Instrumentation Amplifier Configuration ........................................................................... 4 Figure 2. System Block Diagram and Signal Flow .......................................................................... 6 Figure 3. CS4362 ............................................................................................................................ 7 Figure 4. CS8414 Digital Audio Receiver........................................................................................ 8 Figure 5. PCM Input Header ........................................................................................................... 9 Figure 6. DSD Input Header.......................................................................................................... 10 Figure 7. Control Port Interface ..................................................................................................... 11 Figure 8. CDB Mute Control Selection and Routing...................................................................... 12 Figure 9. Channel A1 Output and Mute......................................................................................... 13 Figure 10. Channel B1 Output and Mute....................................................................................... 14 Figure 11. Channel A2 Output and Mute....................................................................................... 15 Figure 12. Channel B2 Output and Mute....................................................................................... 16 Figure 13. Channel A3 Output and Mute....................................................................................... 17 Figure 14. Channel B3 Output and Mute....................................................................................... 18 Figure 15. Power Supply Connections .......................................................................................... 19 Figure 16. Silkscreen Top ............................................................................................................. 20 Figure 17. Top Side....................................................................................................................... 21 Figure 18. Bottom Side.................................................................................................................. 22
LIST OF TABLES
Table 1. System Connections ........................................................................................................ 4 Table 2. CDB4362 Jumper Settings................................................................................................ 5
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts
Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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CDB4362
CDB4362 SYSTEM OVERVIEW
The CDB4362 evaluation board is an excellent means of quickly evaluating the CS4362. The CS8414 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply either PCM or DSD clocks and data through headers for system development. The CDB4362 schematic has been partitioned into 13 schematics shown in Figures 3 through 15. Each partitioned schematic is represented in the system diagram shown in Figure 2. Notice that the system diagram also includes the interconnections between the partitioned schematics. PCM clocks and data. The schematic for the clock/data input is shown in Figure 5. Header J14 allows the evaluation board to accept externally generated DSD data and clock. The schematic for the clock/data input is shown in Figure 6. A synchronous MCLK must still be provided via header J15. Please see the CS4362 datasheet for more information on clocking formats.
4. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by seven binding posts (GND, +5V, VLS, VLC, VD, +18V and -18V), see Figure 15. The VLC and VLS supplies can be jumpered to the +5V binding post for ease of use. VD and VA should be set to the recommended voltages stated in the CS4362 datasheet. +18V and -18V supply power to the op-amps and can be +/-5 to +/-18 volts (must be +/-18 V when filter 2 is selected). WARNING: Refer to the CS4362 datasheet for maximum allowable voltages levels. Operation outside of this range can cause permanent damage to the device.
1. CS4362 DIGITAL TO ANALOG CONVERTER
A description of the CS4362 is included in the CS4362 datasheet.
2. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver, Figure 4. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), and a 256 Fs master clock. The CS8414 data format has been configured for I2S. The operation of the CS8414 and a discussion of the digital audio interface is included in the CS8414 datasheet. The evaluation board has been designed such that the input can be either optical or coax, see Figure 4. However, both inputs cannot be driven simultaneously.
5. GROUNDING AND POWER SUPPLY DECOUPLING
The CS4362 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 3 details the connections to the CS4362 and Figures 16, 17, & 18 show the placement and layout. The decoupling capacitors are located as close to the CS4362 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise.
3. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the 14-pin and 16-pin headers, J14 and J15. Header J15 allows the evaluation board to accept externally generated
6. CONTROL PORT SOFTWARE
The CDB4362 is shipped with Windows 95/98/ME based software for interfacing with the CS4362 control port via the DB25 connector, J1 (Windows NT and 2000 not currently supported). The software can be used to communicate with the CS4362
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CDB4362
in either SPI or I2C mode; however, in SPI mode the CS4362 registers are write-only. contribution of the 2-pole filter which improves the overall dynamic range of the system. The gain of this stage is determined from the following equation:
7. DSD OPERATION
The CDB4362 supports Direct Stream Digital (DSD) operation through the header for external clocks and data, J14. The CS4362 must be placed into the DSD mode and headers J6 and J18 must be set accordingly. See Table 2 for more information.
2( R) GAIN = 1 + ----------R2
The resistor designated by R2 (see Figure 1) can be adjusted to change the gain of the instrumentation amp. The feedback resistors on the two sides of the instrumentation amp `R' must be equal. A resistor divider has been placed before the RCA jack which brings the signal level back to 2 Vrms (selectable per channel with jumpers J21, J22, etc.).
8. ANALOG OUTPUT FILTER
The analog output filter on the CDB4362 has been designed to add flexibility when evaluating the CS4362. The output filter was designed in an optional two stage format, with the first optional stage being an instrumentation amplifier design and the second is a 2-pole butterworth filter. The 2-pole filter is designed to have the in-band impedance matched between the positive and negative legs. It also provides a balanced to single ended conversion for standard un-balanced outputs. The instrumentation amplifier is optionally inserted by changing the FILT jumpers to position 2 (selectable per channel by J37 & 38, J34 & 35, etc.). This instrumentation amplifier incorporates a 5x gain (+14dB) which effectively lowers the noise
CONNECTOR +5V VD VLS VLC -18V +18V GND SPDIF INPUT - J2 SPDIF INPUT - OPTO-1 PCM INPUT - J15 DSD INPUT - J14 PC Port EXT CTRL I/O OUTA1 to OUTB3 INPUT/OUTPUT Input Input Input Input Input Input Input Input Input Input Input Input/Output Input/Output Output
Figure 1. Instrumentation Amplifier Configuration
SIGNAL PRESENT + 5 Volt power + 2.5 to +5V power for the CS4362 digital supply + 1.8 to +5V power for the CS4362 serial interface + 1.8 to +5V power for the CS4362 control interface -18 to -5V negative supply for the op-amps +5 to +18V positive supply for the op-amps Ground connection from power supply Digital audio interface input via coax Digital audio interface input via optical Input for master, serial, left/right clocks and serial data Input for DSD data and clock Parallel connection to PC for SPI / I2C control port signals I/O for SPI / I2C control port signals Channels 1A to 3B line level analog outputs
Table 1. System Connections
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CDB4362
9. ERRATA CDB4362 Revision A.0
The CDB4362 revision A.0 has the following errata. The silk-screens for Z4 and Z5 are reversed. The cathode band marks on the silkscreen are facing the wrong direction. The zener devices have been placed according to the schematic and not the silkscreen.
JUMPER / SWITCH J3 J7 J47 J6 J18 J4 J9 J10 J11 J12 FILT J20 PURPOSE Selects source of voltage for the VLC supplies Selects source of voltage for the VLS supplies Selects source of voltage for the VD supply Clock Source Select Input Mode Select Stand-Alone/Control Port Select M0/AD0/CS M1/SDA/CDIN M2/SCL/CCLK M3/DSD_CLK Filter select MUTEC routing
The three TST pins of the CS4362 (pins 14, 44, and 45) were left floating. As the CS4362 datasheet says, these three pins should be tied to ground.
CDB4362 Revision B.0
The CDB4362 revision B.0 has the following errata. The three TST pins of the CS4362 (pins 14, 44, and 45) were left floating. As the CS4362 datasheet says, these three pins should be tied to ground.
FUNCTION SELECTED Voltage source is VLC binding post Voltage source is +5V binding post Voltage source is VLS binding post Voltage source is +5V binding post Voltage source is VD binding post Voltage source is +5V binding post CS8414 provides PCM inputs to CS4362 PCM or DSD inputs are provided externally Selects PCM input mode Selects DSD input mode (via J16) Stand-Alone Mode (No PC required) Control Port Mode (PC required) See CS4362 datasheet for details See CS4362 datasheet for details See CS4362 datasheet for details See CS4362 datasheet for details Selects standard 2-pole filter Inserts instrumentation-amp MUTEC1 signal is routed to all channels MUTEC1,2,3 is routed per channel pair MUTEC signals are routed for individual mutes Enables the external mute circuit for each channel when 0 Ohm is present (default)
POSITION VLC *+5V VLS *+5V *VD +5V *CS8414 External *PCM DSD SA *CP HI *LO *HI LO *HI LO HI *LO 1 *2 MUTEC1 MUTEC1,2,3 *INDV MUTE *SHUNTED OPEN
0 Ohm after Q1 to Q6
Mute Enables
Table 2. CDB4362 Jumper Settings *Default Factory Settings
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SCLK2 LRCK2
CDB4362
Figure 2. System Block Diagram and Signal Flow
DSD1A DSD1B DSD2A DSD2B DSD3A DSD3B DSD_CLK
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Control Port Figure 7 Reset Circuit
Channel A1 Output and Mute Figure 9 Channel B1 Output and Mute Figure 10 Channel A2 Output and Mute Figure 11 Channel B2 Output and Mute Figure 12 Channel A3 Output and Mute Figure 13 Channel B3 Output and Mute Figure 14
8414 Digital Audio Receiver Figure 4 CS4362 Figure 3
MCLK SCLK1 LRCK1 SDATA1 SDATA2 SDATA3
PCM Inputs
Figure 5
DSD Inputs Figure 6
CDB4362
Figure 3. CS4362
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8
CDB4362
Figure 4. CS8414 Digital Audio Receiver
CDB4362
Figure 5. PCM Input Header
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CDB4362
Figure 6. DSD Input Header
CDB4362
Figure 7. Control Port Interface
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12
CDB4362
Figure 8. CDB Mute Control Selection and Routing
CDB4362
Figure 9. Channel A1 Output and Mute
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14
CDB4362
Figure 10. Channel B1 Output and Mute
CDB4362
Figure 11. Channel A2 Output and Mute
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CDB4362
Figure 12. Channel B2 Output and Mute
CDB4362
Figure 13. Channel A3 Output and Mute
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CDB4362
Figure 14. Channel B3 Output and Mute
CDB4362
Figure 15. Power Supply Connections
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CDB4362
Figure 16. Silkscreen Top
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CDB4362
Figure 17. Top Side
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CDB4362
Figure 18. Bottom Side
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* Notes *

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